Conventional packaged microelectronic devices can include a singulated microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame, and supply voltage, signals, etc., are transmitted to and from the integrated circuit via the bond-pads. In addition to the terminals, the interposer substrate can also include ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.
Packaged microelectronic devices such as those described above are used in cellular phones, pagers, personal digital assistants, computers, and many other electronic products. To meet the demand for smaller electronic products, there is a continuing drive to increase the performance of packaged microelectronic devices, while at the same time reducing the height and the surface area or “footprint” of such devices on printed circuit boards. Reducing the size of high performance devices, however, is difficult because the sophisticated integrated circuitry requires more bond-pads, which results in larger ball-grid arrays and thus larger footprints. One technique for increasing the component density of microelectronic devices within a given footprint is to stack one device on top of another.
One conventional stacking process includes placing a plurality of singulated first dies in a fixture and stacking a plurality of singulated second dies onto corresponding first dies. The stacked first and second dies can then be heated to reflow solder bumps on the second dies and securely attach the second dies to corresponding first dies. The stacked assemblies of first and second dies are then taken out of the fixture and mounted on an interposer substrate (e.g., in a “flip-chip” arrangement). Another reflow process can be used to securely attach the individual stacked die assemblies to the interposer substrate. The stacked die assemblies on the interposer substrate can then be encapsulated and singulated.
The conventional stacking process described above, however, has several drawbacks. For example, the process includes a large number of steps and accordingly can be relatively expensive. The large number of steps can also reduce the throughput of finished devices. Another drawback of the conventional process described above is that the stacked die assemblies can have a relatively large footprint and occupy a significant amount of vertical space (i.e., high profile) because the dies are stacked on an interposer substrate.
Another conventional stacking process includes forming a plurality of first dies on a first support member (e.g., a film frame) and a plurality of second dies on a second support member (e.g., a film frame). The individual first and second dies can be tested while on the support members with a probe device. After testing, the first and second dies are singulated and mounted directly onto an interposer substrate in a stacked configuration. This stacking process, however, also includes several drawbacks. For example, although the dies are tested before singulation to ensure that they function properly, the dies must still undergo a variety of fabrication and packaging processes (e.g., singulation, bumping, mounting) after testing. If the dies become inoperable and/or damaged after these rigorous packaging processes, the entire packaged device (rather than just the bad die) is generally discarded. Accordingly, there is a need to improve the processes for packaging microfeature devices.